The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device with a villus-type capacitor that is capable of increasing the capacitance of a memory cell.
Remarkable developments have been achieved in Dynamic Random Access Memory ("DRAMs") which may be used to further increase the packing density of semiconductor devices, by producing an individual memory cell having a single capacitor and a single transistor. The packing density of semiconductor devices has been quadrupling roughly every three years, along side the progress being made in other areas of semiconductor technology. At present, 4 Mbit DRAMs are in mass production, 16 Mbit DRAMS are in the trial stages for mass production, and 64 Mbit and 256 Mbit DRAMs are under active study for development.
In order to store and retrieve information in a semiconductor memory device, a minimum cell capacitance is required. However, when the packing density of the semiconductor device is increased by a factor four, chip size increases only by 40%. Accordingly, the allotted area for each memory cell is reduced to nearly one third of its previous size. As a result, the conventional capacitor structure is not sufficient for newly-developed memory cells to obtain the required cell capacitance. Therefore, the many problems which are created by the increase in the requisite cell capacitance according to the attainment of higher packing density, remain to be solved.
Two-dimensional planar-type capacitor structures, along with three-dimensional capacitor structures such as trench-type capacitors, stack-type capacitors, and combined stack-trench type capacitors, have all been cited as technologies that may be used to increase the capacitance of memory cells. However, the increased packing density called for in 64 Mbit and 256 Mbit units causes difficulties in achieving sufficient capacitance by the use of simple three-dimensional capacitors. To overcome this problem, a number of modified three-dimensional capacitor structures have been developed, such as the fin-type capacitor structures by Fujutsu Laboratories, the BOX-type (Buried Oxide isolation) capacitor, the SSC (Spread Stacked Capacitor) structures by Toshiba ULSI Laboratories, and cylinder-type capacitor structures by Mitsubishi LSI Laboratories. These capacitors supposedly can attain sufficient cell capacitance for 64 Mbit DRAMs.
On the other hand, a villus-type capacitor structure is formed in such a manner that the storage electrodes formed on source regions are in the shape of pillars whose dimensions are below design rules. Because the capacitance provided by the storage electrodes is formed by sub-design rule pillars, the problem of not achieving sufficient capacitance due to design rules is eliminated. Accordingly, sufficient cell capacitance for 64 Mbit and 256 Mbit DRAMs may be obtained. Mitsubishi Ltd., of Japan has designed a semiconductor memory device having a villus-type capacitor structure.
Conventional semiconductor memory devices having a villus-type capacitor structure are known in the art, and one such type of memory device is illustrated in FIG. 1. A method for manufacturing such villus-type capacitors will be described below in order to provide a better understanding of the present invention.
Referring now to FIG. 1, the conventional semiconductor memory device generally comprises: a field oxide layer 2 for separating an active region from an isolation region of the device; a switching transistor formed of a source region 3, drain region 4 and a gate electrode 6 on an interposing gate oxide layer 5; a storage electrode 11 comprising pillar-shaped electrodes (with dimensions below design rules) in contact with the source region of the switching transistor; a dielectric film 13 that forms a coating over both the source region and the entire pillar-shaped storage electrodes; a second conductive layer 14 covering the whole surface of the dielectric film, forming a plate electrode; an insulating layer 15 adjacent to the upper portions of the second conductive layer and the gate electrode, for isolating the second conductive layer from a bit line; and a bit line 7 formed in contact with drain region 4.
A method for manufacturing a conventional semiconductor memory device with the villus-type capacitor structure is performed as follows.
Gold is implanted through a FIB (Focus Ion Beam) method, using a beam diameter of 0.1 .mu.m in the source region of the switching transistor formed from source region 3, drain region 4, and gate electrode 6 on the interposing gate oxide layer 5. Silicon is then deposited on the device through known deposition methods, such as CVD (Chemical Vapor Deposition) or Vacuum Evaporation. Next, a semiconductor substrate 1 is annealed at very high temperatures, such as 1000.degree. C. The crystallized silicon is then grown in the shape of pillars, but only in the areas where gold has been implanted. Since the gold will have accumulated around the upper portions of the pillars, it can be selectively removed by aqua regia (HNO.sub.3 +HCl) to form the storage electrode composed of the pillars of dimensions below design rules.
A dielectric material is then coated over the whole surface of the pillar-shaped storage electrodes, forming the thin dielectric film 13. A second conductive layer is covered over the dielectric layer to form a plate electrode 14. The insulating layer 15 is formed over both the gate electrode 6 and the plate electrode 14 for isolating the plate electrode 14 from the bit line 7. The bit line 7 is formed by depositing a conductive material covering the drain region 4.
In the conventional semiconductor memory device with the villus-type capacitor structure, the storage electrode is formed by the use of a FIB method without any photolithography process, and restrictions in achieving capacitance due to design rule limitations can be overcome. However, when the FIB method is adopted to form the storage electrodes consisting of pillars, it must be separately conducted for each individual pillar-shaped unit of the electrode of every memory cell. As a result, it takes a considerable amount of time to produce a chip when using this method, and consequently lowers the productivity of the chip-making operation. The villus-type capacitor is therefore, unsuitable for mass production.
Additionally, when the semiconductor substrate 1 is annealed to grow the pillar-shaped electrodes, an impurity-dopant previously implanted in the source region and the drain region may be diffused to the lower portion of the gate electrode by the annealing process. Thus, punch-through occurs, allowing current to directly flow without passing through channel regions, whereby the performance of the device is degraded. Furthermore, the crystalline silicon grown by the annealing process is not formed in the shape of an upright and squared-off pillar with sharp corners, but rather it becomes domed with rounded corners, making it difficult to obtain the desired capacitance.
Accordingly, there is a need for a method of manufacturing villus-type capacitors in semiconductor devices that can obtain the required capacitance of the higher integrated memory devices (64 Mb and higher) while overcoming the problems that make current villus-type capacitors unsuitable for mass production.